Multi-chip packages are high-density packaging technology, i.e., a plurality of vertically stacked chips are packaged inside a package. The current methodology is to stack chips one by one on a wiring substrate and then packaging and testing through the wiring substrate, however, the footprint and the package thickness are increased.
In order to reduce the package dimension of a multi-chip package, conventionally substrates were eliminated by vertically stacking a plurality of wafers in wafer form, then the stacked wafers were singluated into substrate-less multi-chip packages or called “dice cube”, one of relative technologies is disclosed in US Patent No. 2011/0074017 taught by MORIFUJI et al. However, bad chips were inevitably existed in a wafer with random locations from wafer to wafer, therefore, the stacked yield of substrate-less multi-chip packages would be greatly reduced. Moreover, when substrates were eliminated, pitches of the external electrodes and the corresponding testing electrodes of a multi-chip package would become smaller reducing from several hundred micrometer down below 100 um where pogo pins of the conventional package tester can not be implemented for final test. There are two solutions to test chip-stacked packages with smaller-pitch I/O electrodes. One is to surface-mount untested substrate-less chip-stacked packages on a module substrate as an electronic module in advance then to perform module-level testing by skipping package-level testing where the electrical interconnections between the stacked chips in a stacked package can not be screened out before SMT leading to SMT rework or fail. The other one is to prepare untested substrate-less stacked packages firstly, then to surface-mount the package on a wiring interposer usually made of Si with fan-out circuitry and electrodes, then the interposer is loaded into a package tester for final test (FT) and then dismounted from the interposer where the processes are complicated with expensive testing cost.